Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers from inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. The proposed method focuses on gate diffusion input (GDI) which is a low power technique of digital circuit design. Dynamic component of power is reduced in GDI technique as source of PMOS is not permanently connected to Vdd. It also reduces the latency of the circuit. The Viterbi decoder is implemented using GDI cell with 0.25 mm and 90 nm technology with 2.5 V Vdd. Frequency is varied from 15 MHz to 25 MHz. The outputs of the convolutional encoder designed for the constraint lengths K 4, 5, 6, 7 and rate are fed to the designed Viterbi decoder. The comparison results showed 29% reduction in power consumption and 66% reduction in area by using GDI circuit than the CMOS circuit.

An SPICE compatible model for multiple coupled nonuniform lossless transmission lines (TLs) is presented. The method of the modeling is based on the steplines approximation of the nonuniform TLs and quasi-TEM assumptions. Using steplines approximation the system of coupled nonuniform TLs is subdivided into arbitrary large number of coupled uniform lines (steplines) with different characteristics. Then using modal decomposition method the system of coupled partial differential equations for each step is decomposed to a number of uncoupled ordinary wave equations describing uncoupled uniform TLs in each step. To satisfy the boundary conditions at the discontinuities a new model is developed. Therefore each step of the system can be modeled in SPICE using a set of ideal delay lines representing uncoupled TLs and some linear-dependent voltage and current sources. Finally some examples are given to show the validity and usefulness of the model.

Digital transformers are considered as one of the digital Circuits being widely used in signal and data processing systems, audio and video processing, medical signal processing as well as telecommunication systems. Transforms such as Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT) and Fast Fourier Transform (FFT) are among the ones being commonly used in this area. As an illustration, the DCT is employed in compressing the images. Moreover, the FFT can be utilized in separating the signal spectrum in signal processing systems as fast as possible. The DWT is used in separating the signal spectrum in a variety of applications from signal processing to telecommunication systems, as well. In order to build a VLSI circuit, several steps have to be taken from chip design to final construction. The first step in the synthesis of the integrated Circuits is called high-level synthesis (HLS), in which a structural characteristic is obtained from a behavioral or algorithmic description. The resulting structural characteristic is equivalent to the one being considered in the behavioral description and it somehow represents the method for implementing the behavioral description as a result several structural descriptions could be implementable for each behavioral description. Therefore, depending on the intended use, the characteristic will be selected that outperforms the others. The main purpose of the HLS is to optimize the power consumption, the chip occupied area and delayed and is fulfilled by selecting the appropriate number of operating units and how they are implemented to the operators. This is generally accomplished through a graph analysis called the data flow graph (DFG) which is a graphical representation of the type and how the operators connect. In the DFG, each node is equivalent to an operator while the edges represent the relationship between these operators. Experience has proved that if the level of design optimization is high, in addition to higher efficiency, the design time will be lower, which is why the researchers are far more interested in optimization at higher levels of design than the lower levels. The complex, extensive, and discrete nature of the HLS problems have been ranked them among the most complex problems in VLSI Circuits engineering. Bearing this mind, using meta-heuristic and Swarm intelligence methods to solve high-level synthesis projects seems to be a favored option. In this paper, a heuristic method called Moth-Flame Optimization (MFO) has been used to solve the HLS problem in the design of digital transformer to find the optimal response. The MFO is a population-based heuristic algorithm that optimizes the problems using the laws of nature. The leading notion behind the MFO algorithm inspired from the moths’ movements and their instinctive navigation during the night. In the MFO algorithm, the moths are like chromosomes in the GA and like the particles in the PSO algorithm. In order to compare and prove the efficiency of the proposed method, it was applied on the test data with the GA-based method separately but with the same initial conditions. The comparative results along with the results of the GA-based method demonstrated that the proposed method exhibits a higher ability to provide the appropriate hardware structure and high-level synthesis of various types of transformers. Another outstanding feature of the proposed method is its high speed of finding an optimal response with an average of more than 20% greater than the GA based method.

The domain of Very Large Scale Integrated (VLSI) circuit testing has experienced advancements in methodologies for fault detection, which are crucial for addressing the complexities of modern applications. Traditional testing techniques frequently fall short in achieving precise fault localization, highlighting the necessity for the development of enhanced methodologies. This paper endeavors to investigate the implementation of an optimized test generation algorithm aimed at improving testing efficiency and increasing fault coverage. In this study, we utilized a (PSO)-enhanced FAN (fan-out-oriented algorithm) applied to ISCAS'89 benchmark Circuits. The optimization process involved refining the decision trees utilized in the FAN algorithm through a rigorously defined cost function, which strikes a balance between accuracy, complexity, and operational efficiency. The results indicate improvement in both fault coverage and detection efficiency. Furthermore, the optimization process resulted in a reduction of required test vectors, thereby enhancing testing efficiency, particularly in high-volume production environments. The study also introduces the development of diagnostic metrics that provide deeper insights into circuit failures and proposes design-for-testability techniques to improve reliability. The integration of PSO within the FAN algorithm not only facilitates the generation of robust test solutions but also produces high-quality test vectors.

VLSI technology is currently dealing with a serious challenge, as the exponential growth of density in VLSI and CMOS chips has reached its limit. Power dissipation in VLSI chip refers to heat generation, which is a real barrier against traditional CMOS technology. Irreversible logic leads to problems such as energy dissipation, heat generation, information loss and slow computations. We need a new technology for solving these problems. Using reversible logic can help solve this problem. In next generation of optical computers, electrical Circuits and wires will be replaced by several optical fibers and these systems will be more efficient because they will be cheaper, lighter, and more compact without interference. Based on optical computations, several optical switches have been proposed for future applications. One of these switches is the Mach-Zehnder switch. Its behavior and the reversible Circuits, which can be made with this switch is studied in this article. Finally, we introduce and design three new all-optical reversible gates named NFT, SRK and MPG, which are effective in designing all-optical reversible logical Circuits such as flip-flops and other all-optical reversible sequential Circuits. We also simulate one all-optical reversible Circuits implemented with Mach-Zehnder switch and provide simulation challenges and solutions to overcome these challenges.

This paper proposes the efficient VLSI architecture of camera distortion correction, based on a Neural Camera Distortion Model (NCDM). Conventional imaging methods use over two kinds of models to correct the camera and lens distortions, but the NCDM uses a single model to immediately correct the geometry distortion and unsymmetrical manufacturing errors. The NCDM, with four neurons, performs a wide-angle distortion correction. The results show that the maximal corrected error in a whole image is less than 1.1705 pixels, and the MSE approaches 0.1743 between corrected and ideal results. The distortion correction by NCDM is 429more accurate than the conventional approach. The chip size of NCDM is 1: 51×1: 51 mm2 and contains 126 K gates using the TSMC 90 nm CMOS technology process. Working at 240 Mhz, this architecture can correct 30 frames and a Full-HD resolution video per second. Results show that the maximal corrected error in a whole image is less than 1.4 pixels, and the mean square error approaches 0.0376 between corrected and ideal results.

Since, the characteristics of VLSI basic Circuits like XOR/XNOR which are the result of single cell simulation setup, are not necessarily defining their behavior in multistage Circuits, so reaching to different test methods and more suitable patterns are important issues for investigators in this field. In this paper a new method is proposed in which timing behavior of different Circuits can be determined and compared so the result can be used in different structure configurations and large scale Circuits. In addition to the new algorithm for designing XOR/XNOR balance Circuits, two more new Circuits have been proposed. By simulation tool, HSPICE, first sizing transistor due to PDP characteristics for Circuits has been done and then their timing behaviors have been compared. The optimal circuit due to timing behavior is one of the novel methods. Simulations have been done by 0.18mm tmtechnology on the base of BS2M3v model.

Computation of the second order delay in RC-tree based Circuits is important during the design process of modern VLSI systems with respect to having tree structure Circuits. Calculation of the second and higher order moments is possible in tree based networks. Because of the closed form solution, computation speed and the ease of using the performance optimization in VLSI design methods such as floor planning, placement and routing, the Elmore delay metric is widely implemented for past generation Circuits. However, physical and logical synthesis optimizations require fast and accurate analysis techniques of the RC networks. Elmore first proposed matching circuit moments to a probability density function (PDF), which led to the widespread implementation of it in many networks. But the accuracy of Elmore metric is sometimes unacceptable for the RC interconnect problems in today’s CMOS technologies. The main idea behind our approach is based on the moment matching technique with the power-lognormal distribution and proposing the closed form formula for the delay evaluation of the RC-tree networks. The primary advantages of our approach over the past proposed metrics are the ease of implementation, reduction of the complexity and proposing an efficiency formula without referring to lookup tables. Simulation results confirmed that our method illustrates a good degree of accuracy and the relative average of errors is less than 20%.